Topic:14nm, 7nm and beyond: bring industry design challenges to academic world
Owner:Ou He
Senior Engineer in Chip Design and Methodology, Ph.D in EDA labs, Dept of Computer Science and Technology, Tsinghua University
Served in IBM, Pinecone (XiaoMi) and GlobalFoundries. 10 year experience in industry. Involved in a variety of chips like network, cellphone and etc. Acquainted with chip planning, PR, timing, Power, EM&IR, packaging and other subdomain. Knowledge on general EDA algorithms with publications on top conference and journals in Design Automation. Currently working and leading the study on some basic design problems for 16nm, 14nm and 7nm, as well as on the development of back-end flows.
Time：10:00 May 23rd,2018
Place: 微电子大楼105教室
Abstract: As technology node gets closer to the Moore’s limit, a large amount of chip fabrication challenges are translated to physical design challenges. They are quickly becoming the focus of both EDA vendors and academic researches. However, there is always a gap among chip designers, EDA tools and research articles.
This lecture will give an overall introduction on the challenges in current advanced node from a chip designer’s perspective. Meanwhile, it will also show the current status of the major industry EDA vendors and propose topics to the academic students.
