Title: From Communication Algorithm to VLSI Architecture: Algorithm-Architecture Codesign for Digital Baseband Receiver
Speaker: Dr Zhifeng WU
Department of Electronic Engineering
National Chao Tung University, Hsinchu, Taiwan
Host: Dr Guoxing Wang
When: 10:00 – 11:00, May 14, 2014
Where: Room 401, Building of School of Microelectronics
Abstract:
Both the communication algorithm and the VLSI architecture of baseband receiver in wireless orthogonal frequency-division multiplexing (OFDM) systems are crucial to determine the system performance and the hardware complexity. Significantly, the algorithm-architecture codesign approach for the digital baseband receiver can indeed yield not only superior system performance but also cost-efficient hardware. In this talk, the joint carrier synchronization and channel equalization algorithm is introduced as a demonstration of the algorithm-architecture codesign approach for OFDM baseband receiver. In order to obtain the cost-efficient hardware, a CORDIC-based VLSI architecture is proposed to realize the joint algorithm for OFDM baseband receiver. Finally, a field-programmable gate array (FPGA) prototyping of the OFDM baseband receiver is used to be a test vehicle to examine the system performance and the hardware complexity.
In the first part of this talk, considering both system performance and computational complexity, a single cost function of joint algorithm is presented to minimize the mean-square error (MSE) on each subchannel and further to lower the BER. The joint algorithm is constructed by the carrier synchronization and the channel equalization schemes. Physically, the carrier synchronization scheme is a dual-loop structure, which is composed of outer and inner loops to cope with the carrier frequency offset (CFO) and the channel phase variation. Besides, a gain equalization loop is employed to compensate the magnitude distortion on each subchannel. The relationship between the system performance and the closed-loop jitter for the joint algorithm is explored. Many simulations were done for the additive white Gaussian noise (AWGN) and the multipath frequency-selective fading channel to prove the consistency with the performance analysis and further to show that the joint algorithm can accurately estimate and compensate the CFO and the channel distortion.
In the second part, the CORDIC-based VLSI architecture is conducted to realize the joint algorithm and simultaneously to obtain the cost-efficient hardware. In addition, the fixed-point analysis is derived to acquire the precise signal path in hardware design. Finally, a video demonstration of FPGA prototyping for wireless OFDM receiver exhibits that the algorithm-architecture codesign approach can really acquire not only superior system performance but also cost-efficient hardware.
Biography:
Dr. Wu received the B.S. degree in 1995 from the Department of Electronic Engineering, National Yunlin University of Science and Technology (formerly National Yunlin Institute of Technology), Yunlin, Taiwan, the M.S. degree in 1998 from the Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, and the Ph.D. degree in 2011 from the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. Currently, he is a Post-doc in the Department of Electronic Engineering, National Chao Tung University, Hsinchu, Taiwan, where he is responsible for the digital baseband communication algorithm and its related VLSI architecture design for 60 GHz transmission system. He is also an Adjunct Assistant Professor with the Department of Applied Electronics Technology, National Taiwan Normal University, Taipei, and the Department of Electrical Engineering, National United University, Miaoli. His research interests include wireless communication systems, digital subscriber loop technologies, digital communication signal processing, carrier/timing synchronization and channel equalization techniques for OFDM and DMT systems, and the related integrated circuit design for the digital baseband communication systems.
He has held industrial positions with Holteck Semiconductor Inc. (新竹科學園區/合泰半導體) in Hsinchu Science Park (1995-1996), where he was an ASIC designer, the Computer & Communications Research Laboratories (CCL), Industrial Technology Research Institute (工業技術研究院(ITRI)/電腦與通訊研究所) in Hsinchu (1998-2000), the IC Plus Corp. (凱訊電子) in Hsinchu (2000) and the Trendchip Technologies Corp. (誠致科技) in Hsinchu (2001-2002), where he was responsible for the design of the time-domain equalizer (TEQ) and the time-domain integration of ADSL transceiver chipset, as well as interoperability test (IOT). He was a Technical Associate Manager in the digital IC department of Trendchip Technologies Corp. in 2002. He also was one of founder of Trendchip Corp. From 2011 to 2012, he was a system designer (Technical Staff) at the Wireless Broadband Technology Division, Information & Communication Research Laboratories (ICL), ITRI (工業技術研院/資訊與通訊研究所), Hsinchu, where he was involved in the physical-layer design of femtocell for 4G LTE system.
Currently, Dr. Wu is involved in the publication co-chair and TPC member of IEEE international conference on consumer electronics-Taiwan (ICCE-Taiwan) 2014. Dr. Wu also serves as the reviewers of IEEE Trans. on Communications, IEEE Trans. on Vehicular Technology, IEEE Trans. on Circuits and Systems – Part I, IEEE Trans. on Communications Letters, IEEE Consumer Electronics Magazine, IEEE Global Communications Conference (GLOBECOM), IEEE Vehicular Technology Conference (VTC) and IEEE International Symposium on Personal, Indoor and Mobile Radio Communication (PIMRC).
