孙亚男 / 副教授
孙亚男博士，现任上海交通大学微纳电子学系副教授。2009年获得上海交通大学微电子学本科学位，2015年获得香港科技大学电子及计算机工程学博士学位，同年加入上海交通大学，从事教学与科研工作。孙亚男博士的主要研究方向是基于新型纳米技术的高能效及高良率集成电路及系统设计。研究成果发表在IEEE TCAS-I, TCAS-II, TCAD, TED, TVLSI, TDMR等国际期刊，以及ISCAS, DATE, ICM等国际会议上，曾获2020年IEEE DATE（欧洲设计自动化与测试学术会议）最佳论文提名奖，2014年IEEE ICM（微电子国际会议）的最佳论文奖。IEEE会员，并担任多个国际期刊和会议的审稿人。自2015年起，担任国际期刊Microelectronics Journal的副主编（Associate Editor）。
Dr. Yanan Sun is currently an Associate Professor in the Department of Micro-Nano Electronics at Shanghai Jiao Tong University. She received the B.E. degree in Microelectronics from Shanghai Jiao Tong University in 2009, and the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2015. Dr. Sun’s research area is high energy-efficient and high-yield circuit and system design with emerging nanotechnologies. Her research works are published in the international journals, such as IEEE TCAS-I, TCAS-II, TCAD, TED, TVLSI, and TDMR, as well as the international conferences, such as ISCAS, DATE, and ICM. She received the best paper award nomination in 2020 IEEE Design, Automation, and Test in Europe Conference (DATE) , and the best paper award (first place) in 2014 IEEE International Conference on Microelectronics (ICM). Dr. Sun is a member of IEEE. She also served as a reviewer for multiple international journals and conferences. She serves as an associate editor on the editorial boards of the Microelectronics Journal since 2015.
 Z. Song, Y. Sun*, L. Chen, T. Li, N. Jing, X. Liang, and L. Jiang*, “ITT-RNA: Imperfection tolerable training for RRAM-crossbar based deep neural-network accelerator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 2020.
 Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Monolithic 3D carbon nanotube memory for enhanced yield and integration density,” IEEE Transactions on Circuits and Systems I (TCAS-I), March 2020.
 Y. Sun, J. Gu, W. He, Q. Wang, N. Jing, Z. Mao, W. Qian, and L. Jiang, “Energy-efficient nonvolatile SRAM design based on resistive switching multi-level cells,” IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 66, No. 5, pp. 753-757, May 2019.
 Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-CN-removal-tolerant high-yield six-CNMOSFET SRAM cell for carbon-based embedded memory,” IEEE Transactions on Electron Devices (TED), Vol. 65, No. 3, pp. 1230-1238, March 2018.
 Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “High-yield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes,” IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, pp. 20-31, March 2017.
 Y. Sun, W. He, Z. Mao, and V. Kursun, “Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic,” Microelectronics Journal (MEJ), Vol. 62, pp. 12-20, February 2017.
 Y. Sun, H. Jiao, and V. Kursun, “A novel robust and low-leakage SRAM cell with nine carbon nanotube transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
 Y. Sun and V. Kursun, “Carbon nanotubes blowing new life into NP dynamic CMOS circuits,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 2, pp. 420-428, February 2014.
 C. Ma, Y. Sun*, W. Qian, L. Jiang, and R. Yang, “Go unary: A novel synapse coding and mapping scheme for reliable ReRAM-based neuromorphic computing,” Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), March 2020. (Nominated for Best Paper Award).
 C. Lin, W. He, Y. Sun, B. Pei, Z. Mao, and M. Seok, “A near-threshold-voltage network-on-chip with a metastability error detection and correction technique for supporting a quad-voltage/frequency-domain ultra-low-power system-on-a-chip,” Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), February 2020.
 J. Jiang, Y. Sun*, W. He, Z. Mao, and V. Kursun, “Carbon-based three-dimensional SRAM cell with minimum inter-layer area skew considering process imperfections,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 1-4, October 2019.
 Y. Lu, Y. Sun*, W. He, and Z. Mao, “A novel memristor-reusable mapping methodology of in-memory logic implementation for high area-efficiency,” Proceedings of the IEEE/ACM International Symposium on Nanoscale Architecture, June 2019.
 Y. Sun, Wei. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 908-911, October 2017. (invited)
 N. Jing, T. Li, Z. Zhao, W. Jin, Y. Sun, W. He, and Z. Mao, “Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory,” International Conference on Field-Programmable Technology (FPT), pp. 233-236, December 2016.
 Y. Sun and V. Kursun, “Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2720-2723, May 2015.
 Y. Sun, H. Jiao, and V. Kursun, “Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins,” Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014. (Best paper award – first place)
１. 最佳论文提名奖, IEEE DATE 2020.
２. 优秀指导教师奖, 全国大学生集成电路创新创业大赛, 2019.
３. 上海交通大学电院第二届青年教师教学竞赛-三等奖(英语组), 2018.
４. 上海交通大学优秀班主任, 2018.
６. 优秀指导教师奖, 北京大学生集成电路设计大赛暨全国邀请赛, 2016.
７． 最佳论文奖,IEEE ICM 2014.