| Journal Articles |
| G. Shi,“A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits,”Analog Integrated Circuits and Signal Processing, 2011, Springer online first. |
| Z. Hao, S. Tan, E. Tlelo-Cuautle, W. Yu, Y. Cai and G. Shi,“Statistical Extraction and Modeling of Inductance Considering Spatial Correlations,”Analog Integrated Circuits and Signal Processing Journal (AISPJ), 2011, Springer online first. |
| G. Shi, “Computational Complexity Analysis of Determinant Decision Diagram,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.57, no.10, pp.828-832, Oct. 2010 |
| Conference Proceedings |
| H. Zhang and G. Shi, “Symbolic behavioral modeling for slew and settling analysis of operational amplifiers,” Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on, 7-10 Aug. 2011, vol., no., pp.1-4. |
| Z. Hao , Sheldon X.-D. Tan, R. Shen and G. Shi, “Performance Bound Analysis of Analog Circuits Considering Process Variations”, Proc. IEEE/ACM Design Automation Conference ( DAC ),San Diego, 5-10 June 2011. |
| Z. Hao , S. Tan and G. Shi, “Statistical Full-Chip Dynamic Power Estimation Considering Spatial Correlations”, Proc. International Symposium on Quality Electronic Design ( ISQED ), Santa Clara, 14-16 Mar. 2011. |
| Z. Hao , R. Shen, S. Tan, B. Liu, G. Shi and Y. Cai, “An Efficient Statistical Chip-Level Total Power Estimation Method Considering Process Variations with Spatial Correlation”, Proc. International Symposium on Quality Electronic Design (ISQED), Santa Clara, 14-16 Mar. 2011. |
| H. Xu, G. Shi and X. Li, “Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps,” Asia South-Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan. 2011, pp. 19-24. |
| X. Li, H. Xu, G. Shi, and A. Tai, “Hierarchical symbolic sensitivity computation with applications to large amplifier circuit design,” Proc. International Conference on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 2011, pp. 2733-2736. |
| Z. Hao and G. Shi, “A Fast Symbolic Computation Approach to Statistical Analysis of Mesh Networks with Multiple Sources”, Proc. Asia and South Pacific Design Automation Conference (ASPDAC), Taiwan, 18-21 Jan. 2010, pp.383-388. |
| D. Ma, G. Shi and A. Lee, “A design platform for analog device size sensitivity analysis and visualization,” Asia South-Pacific Circuits and Systems Conference (APCCAS), Malaysia, Dec. 2010, pp. 48-51. |
| G. Shi, “A simple implementation of determinant decision diagram,” Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on ,7-11 Nov. 2010, vol., no., pp.70-76. |
| Z. Hao and G. Shi, “Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees,” Proc. IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Cancún, México, Aug. 2009, pp. 212-215. |
| Z. Hao and G. Shi, “Symbolic techniques for statistical timing analysis of RCL mesh networks with resistor loops,” Proc. IEEE International Symposium on Integrated Circuits (ISIC), Singapore, 14-16 Dec. 2009, pp. 470-473. |
| G. Shi and X. Meng, “Variational analog integrated circuit design via symbolic sensitivity analysis,” Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on , 24-27 May 2009, vol., no., pp.3002-3005, |
| G. Shi and X. Meng , “Variational analog integrated circuit design by symbolic sensitivity analysis,” Proc. International Symposium on Circuits and Systems (ISCAS), Taiwan, China, May 2009, pp. 3002-3005 . |
| Z. Hao and G. Shi, “New approaches to interconnect macromodeling with explicit delay extraction,” Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, Dec. 2008, pp. 1546-1549. |
| Z. Hao and G. Shi, “Parametric analysis of multiple interconnects via canonical reduced order modeling,” Proc. IEEE International Conference on ASIC (ASICON), Guilin, China, Oct. 2007, pp. 1133-1137. |
| G. Shi, W. Chen, and C. Shi, “A graph reduction approach to symbolic circuit analysis,” Proc. Asia South-Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2007, pp. 197-202. |
| W. Chen and G. Shi, “Implementation of a symbolic circuit simulator for topological network analysis,” Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, Dec. 2006, pp. 1327-1331. |