1.重点研发“高性能抗量子攻击密码芯片技术”，参与，2023-2026。

2.重点研发“存算一体器件及其计算新架构”，参与，2019-2024。

3.自然科学基金“粗粒度可重构架构的软错误自适应防护模型与方法研究”，项目负责人，2013-2015。

4.十二五863项目“面向通用计算的可重构处理器关键技术研发”，参与，2012-2015。

5.十一五863项目“嵌入式可重构移动媒体核心处理技术”，参与，2009-2012。

[1] Yang W., Yang Y., Ji S., Jiang J., Jing N., Wang Q., Mao Z., Sheng W. RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024,43(10): 2854-2867.

[2] Yang Y., Yang W., Wang Q., Jing N., Jiang J., Mao Z., Sheng W. An Efficient Near-Bank Processing Architecture for Personalized Recommendation System. 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC). 2023: 122-127.

[3] Zhao Z., Sheng W., Li J., Ye P., Wang Q., Mao Z. Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA[J]. Electronics, 2021,10(18): 2210.

[4] Zhao Z., Sheng W., Wang Q., Yin W., Ye P., Li J., Mao Z. Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling[J]. IEEE Transactions on Parallel and Distributed Systems, 2020,31(9): 2201-2219.

[5] Zhang Y., Sheng W., Jiang J., Jing N., Wang Q., Mao Z. Priority Branches for Ship Detection in Optical Remote Sensing Images[J]. Remote Sensing, 2020,12(7): 1196.

[6] Zhongyuan Z., Hyoukjun K., Kuhar S., Weiguang S., Zhigang M., Krishna T. mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator[J]. 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Proceedings, 2019: 282-292.

[7] Wang Q., Shen F., Shen L., Huang J., Sheng W. Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network[J]. Journal of Digital Imaging, 2019,32(6): 971-979.

[8] Zhao Z., Liu Y., Sheng W., Krishna T., Wang Q., Mao Z. Optimizing the data placement and transformation for multi-bank CGRA computing system. 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018: 1087-1092.

[9] Xie S., Zhao Z., Sheng W., Wang Q., Mao Z. MBSS:A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig). 2018: 1-8.

[10] Zhao Z., Sheng W., He W., Mao Z., Li Z. A static-placement, dynamic-issue framework for CGRA loop accelerator. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017: 1348-1353.

[11] Sheng W. G., Jiang J. F., Mao Z. G. Parallel SER analysis for combinational and sequential standard cell circuits[J]. Microelectronics Journal, 2016,50: 8-19.

[12] Zhao Z., Sheng W., Jing N., He W., Mao Z. Resource-saving compile flow for coarse-grained reconfigurable architectures. 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). 2015: 1-8.

[13] Sheng W., He W., Jiang J., Mao Z. Pareto optimal temporal partition methodology for reconfigurable architectures based on multi-objective genetic algorithm. 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012, May 21, 2012 - May 25, 2012. Shanghai, China: IEEE Computer Society, 2012: 425-430.

[14] Sheng W., Xiao L., Mao Z. Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC '09). 2009: 502-507.