论文发表

[1]P. Ji, J. Gao, W. Xu, Y. Sun, W. He, and H. Wu, “Electronic-photonic integrated circuit design and crosstalk modeling for a high density multi-lane MZM array,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.

[2]C. Wang, Y. Sun, S. Hu, L. Jiang, W. Qian, “Variation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit,” ACM Transactions on Design Automation of Electronic Systems, Vol. 23, No. 4, pp. 1-27, June 20

[3]Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-CN-removal-tolerant high-yield six-CNMOSFET SRAM cell for carbon-based embedded memory,” IEEE Transactions on Electron Devices (TED), Vol. 65, No. 3, pp. 1230-1238, March 2018.

[4]Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang, “CNFET-Based High Throughput SIMD Architecture”, in IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 37(7): 1331-1344, 2018.

[5]Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, and Naifeng Jing*, “IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs”, accepted by IEEE Transaction on Parallel and Distributed Systems (TPDS), 29(3): 586-599, 2018.

[6]Zhuojun Liang, Chunhui Ding, Guanghui He: A Low-Complexity Signal Detection Approach in Uplink Massive MIMO Systems. IEICE Transactions on Fundamentals. Jul. 2018.

[7]Mingyi Chen, Min Wang, Hengwei Yu, Guanghui He, Yongxin Zhu, Yadong Liu, Guoxing Wang: A Self-Powered 3.26-μW 70-meter Wireless Temperature Sensor Node for Power Grid Monitoring. IEEE Trans. on Industrial Electronics 2018

[1] Z. Zhao, W. Sheng, W. He, Z. Mao, and Z. Li, "A static-placement, dynamic-issue framework for CGRA loop accelerator," Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1348-1353, 2017.

[2]X. Jin, W. Jin, H. Zhang, J. Jiang, and W. He, "A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May

[3]L. Hu, J. Gu, G. He, W. He， “A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications，” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2017.

[4]J. Gao, Y. Sun, W. He, and H. Wu, “A cross-layer multi-physics design flow for electronic-photonic integrated circuits,” IEEE Photonics Conference (IPC), pp. 230-231, January 2017.

[5]W. Xu, J. Gao, P. Ji, Y. Sun, W. He, and H. Wu, “A PAM-4 optical receiver based on a silicon photonic quantizer,” IEEE International Conference on Group IV Photonics (GFP), August 2017.

[6]L. Chen, Y. Sun, and W. He, “Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 916 - 919, October 2017. (invited)

[7]Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 908 - 911, October 2017. (invited)

[8] Y. Ding, W. Jin, G. He, and W. He, "Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage," Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 985-988, October 2017.

[9]W. Jin, G. He, W. He, and Z. Mao, "A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras," Integration, the VLSI Journal, Vol. 59, pp. 206-217, September 2017.

[10]W. Jin, W. He, J. Jiang, H. Huang, X. Zhao, Y. Sun, X. Chen, and N. Jing, “A 0.33V 2.5μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130nm CMOS,” Integration, the VLSI Journal, Vol. 58, pp. 27-34, February 2

[11]W. Jin, S. Kim, W. He, Z. Mao and M. Seok, "In situ error detection techniques in ultralow voltage pipelines: Analysis and optimizations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 3, pp. 1032-1043, March 2017.

[12]Y. Sun, W. He, Z. Mao, and V. Kursun, “Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic,” Microelectronics Journal, Vol. 62, pp. 12-20, April 2017.

[13]Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “High-yield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes,” IEEE Transactions on Device and Materials Reliability, Vol. 17, No. 1, pp. 20-31, March 2017.

[14]W. Jin, S. Kim, W. He, Z. Mao, and M. Seok, "Near- and Sub-Vt pipelines based on wide-pulsed-latch design techniques," IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 9. pp. 2475-2487, September 2017.

[15]Chaoyang Li, Qin Wang, Jian-Fei Jiang, Nin Guan:A metastability-based true random number generator on FPGA. ASICON 2017: 738-741

[16]Xianjie Long,Qin Wang,Jian-Fei Jiang,Nin Guan:An on-chip circuit for timing measurement of SRAM IP. ASICON 2017: 569-572

[17]Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao，Dynamic data split: a Crosstalk Suppression Scheme in TSV-Based 3D IC，Integration, the VLSI Journal 59 (2017) 23–30.

[1]Jiayi Hu, *Qin Wang, Jianfei Jiang, Jing Xie, Zhigang Mao. “A Crosstalk Avoidance Scheme Based on Re-layout of Signal TSV”, The IEEE 11th International Conference on ASIC, 2015. EI Accession number: 20163402733718 [7]Sai Hu, *Qin Wang, Zheng Guo, Jing Xie

[2]Qifan Hu, *Qin Wang, Jing Chen, Jing Xie, Zhigang Mao, TSV-to-TSV Crosstalk Induced Delay Analysis for 3D ICs, IEEE 13th International Conference on Solid-State and Integrated Circuit Technology(ICSICT). 2016

[3]Mengying Fan,QinWang, Ben van der Waal, Wafer Defect Patterns Recognition Based on OPTICS and Multi-Label Classification, 2016 IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference(IEEE IMCEC 2016 )

[4]Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, “Contactless Testing Methodology for Pre-bond Interposer,” IEEE 58th International Midwest Symposium on Circuits and Systems (MWSWCAS), 2015. SCI收录号WOS:000370979500062 ; EI Accession number: 201614022

[5]Jianfei Jiang, Zhigang Mao, Weiguang Sheng，Qin Wang，Weifen He “Design Optimization for Low Swing RC-Limited Global Interconnect”, Journal of Circuits, Systems and Computers SCI收录号WOS:000381393100008 ;EI Accession number:20162202446351

[6]Jiachao Chen, *Qin Wang, Zheng Guo, “A Circuit Design of SMS4 against Chosen Plaintext Attack”,2015 International Conference on Computational Intelligence and Security (CIS'2015) . SCI收录号 WOS:000380584700088;EI Accession number:20161802318747

[1]Y. Sun and V. Kursun, “Carbon-based sleep switch dynamic logic circuits with variablestrength keeper for lower-leakage currents and higher-speed,” Proceedings of the IEEEInternational Symposium on Circuits and Systems (ISCAS), pp. 2720-2723, May 2015.

[2]Y. Sun, H. Jiao, and V. Kursun, “A novel robust and low-leakage SRAM cell with ninecarbon nanotube transistors”, IEEE Transactions on Very Large Scale Integration (VLSI)Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.

[3]Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, “Contactless TestingMethodology for Pre-bond Interposer,” IEEE 58th International Midwest Symposium onCircuits and Systems (MWSWCAS), 2015.

[4]Jianfei Jiang, Weifeng He, Qin Wang, Zhigang Mao, “Design Optimization for Capacitive-resistively Driven On-chip Global Interconnect,” IEICE Electronics Express, Vol.12, No.8, p1-12, 2015.

[5]T. Dickson, Yong Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss, H. Ainspan, A. Rylyakov, B. Parker, C. Baks, L. Shan, Y. Kwark, J. Tierno, and D. Friedman, “A 1.4-pJ/b, Power-Scalable 16x12-Gb/s Source-Synchronous I/O with DFE R

[1]Y. Sun and V. Kursun, “Carbon nanotubes blowing new life into NP dynamic CMOS circuits,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 2, pp. 420-428, February 2014.

[2]Y. Sun, H. Jiao, and V. Kursun, “Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins”, Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014 (Best paper award - first place).

[3]W. Sheng, W. He, J. Jiang, and Z. Mao, "Full Automatic Task Compilation Flow from C to REmus Coarse Grain Reconfigurable Media Processor," Journal of Convergence Information Technology, vol. 6, pp. 193-202, 2012.

[4]W. Sheng, W. He, J. Jiang, and Z. Mao, "Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm," presented at the 19th Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, 20

[5]W. Sheng, W. He, and Z. Mao, "A Template Based Task Mapping Framework for Coarse Grain Reconfigurable Multimedia Processor," Journal of Computational Information Systems, vol. 8, pp. 159-167, 2012.

[6]T. Dickson, Yong Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss,H. Ainspan, A. Rylyakov, B. Parker, C. Baks, L. Shan, Y. Kwark, J. Tierno, and D. Friedman, “A 1.4-pJ/b, Power-Scalable 16x12-Gb/s Source-Synchronous I/O with DFE Re

[1]Lei Zeng, Xin Yi, Sheng Lu, Yuan Lou, Jianfei Jiang,Hongen Qu, Ning Lan, Guoxing Wang, "Design of a high voltage stimulator chip for a stroke rehabilitation system, IEEE Conference on Engineering in Medicine and Biology Society (EMBC), pp. 834-837, 2013.

[2]Zhenyang Chen,Qin Wang, Jing Xie, Jin Tian, Jianfei Jiang ,"Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling", Circuits and 2013 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2646-2649, 2013.

[3]Zhenyang Chen, Qin Wang, Jing xie Modeling and Analysis of Signal Transmission with Through Silicon via (TSV) Noise Coupling ISCAS2013

[4]Zhenyang Chen,Wangqin,etc “Modeling and Analysis of Signal Transmission with ThroughSilicon Via (TSV) Noise Coupling (ISCAS2013)

[5]N. Sun, Y. Liu, L. Qin, H. Lee, R. M. Westervelt, and D. Ham, “Small NMR Biomolecular Sensors," (Invited paper) Journal of Solid-State Electronics, pp. 13-21, June 2013.

[6]B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishan, D. Friedman, and M. Ritter, “Specifications of Nanoscale Devices and Circuitsfor Neuromorphic Computational Systems,”IEEE Transactions on Electron Devices, pp. 246-253, Jan. 2013.

[7]B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishan, D. Friedman, and M. Ritter, “RRAM Devices for Large Neuromorphic Systems,” Non-Volatile Memories Workshop, UCSD, March, 2013.

[8]M. Sanduleanu, A. Valdes-Garcia, Y. Liu, B. Parker, S. Shlafman, B. Sheinman, D. Elad, S. Reynolds and D. Friedman, “A 60GHz, Linear, Direct Down-Conversion Mixer with mm-Wave Tunability in 32nm CMOS SOI,” IEEE Custom Integrated Circuits Conference(CICC)

[9]Y. Liu, P. Hsieh, S. Kim, J. Seo, R. Montoye, L. Chang, J. Tierno, and D. Friedman, “A0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI,” IEEE International Solid-State Circuits Conference (ISSCC) Digest of

[1]Kan Yuan，Dawu Gu*，Zheng Guo，Sigang Bao，A Highly Eifficient Differential Power Analysis on PRINTcipher，The 8th International Conference on Computational Intelligence and Security (CIS 2012) , 2012.11，Guangzhou

[2]Shunqing Yan, Liang Hong, Weifeng He and Zhigang Mao, Group-Based Fast Decision Algorithm for Intra Prediction in HEVC, Proc. of the 8th Signal-Image Technology and Internet-Based Systems (SITIS) 2012

[3]Shunqing Yan, Yongxin Zhu, Qiannan Zhang, Qin Wang, Ming Ni and Guangwei Xie, A Case Study of CPNS Intelligence: Provenance Reasoning over Tracing Cross Contamination in Food Supply Chain, Proc. of the 32nd International Conference on Distributed Systems

[4]N. Sun, Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “Silicon RF NMR biomolecular sensor - Review," (Invited paper) Proceedings of European Solid-State Device Research Conference (ESSDERC), pp. 14-17, Sept. 2012.

[5]A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, and D. Friedman, “A 19Gb/s Serial Link Receiver with Both 4-Tap FFE and 5-Tap DFE Functions in 45nm SOI CMOS,”ISSCC Dig. of Tech. Papers, pp. 134-135, Feb. 2012.

[6]Y. Liu, W. Luk, and D. Friedman, “A Compact Low-Power 3D I/O in 45nm CMOS,” ISSCC Dig. of Tech. Papers, pp. 142-143, Feb. 2012.

[7]T. Dickson, Y. Liu, S. Rylov, B. Dang, C. Tsang, P. Andry, J. Bulzacchelli, H. Ainspan, X. Gu,L. Turlapati, M. Beakes, B. Parker, J. Knickerbocker, and D. Friedman, “An 8x10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Intercon

[8]J. Knickerbocker, P. Andry, E. Colgan, B. Dang, T. Dickson, X. Gu, C. Haymes, C. Jahnes, Y. Liu, J. Maria, R. Polastre, C. Tsang, L. Turlapati, B. Webb, L. Wiggins and S. Wright, “2.5D and 3D Technology Challenges and Test Vehicle Demonstrations,” IEEE El

[9]X. Gu, J. Silberman, Y. Liu and X. Duan, “Mitigating TSV-induced Substrate Noise Coupling in 3-D IC Using Buried Interface Contacts,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 75-78, 2012.

[10]A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, and D. Friedman, “A 19Gb/s Serial Link Receiver with Both 4-tap FFE and 5-tap DFE Functions in 45nm SOI CMOS,” (Special issue paper) IEEE Journal of Solid-State Circuits (JSSC), pp. 3220-3231, De

[1]H. Wang, W. Sheng, and W. He, "Automatic compilation flow for a coarse-grained reconfigurable processor," in IEEE 9th International Conference on ASIC (ASICON'11), 2011, pp. 687-690.

[2]Y. Zhou, W. Sheng, X. Liu, W. He, and Z. Mao, "Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm," in IEEE 9th International Conference on ASIC (ASICON'11), 2011, pp. 941-944.

[3]Wang, Bin; Xie, Jing; Mao, Zhigang; Wang, Qin; Multiple continuous error correct code for high performance network-on-chip. Microelectronics and Electronics （PrimeAsia）, 2011 Asia Pacific Conference on Postgraduate Research in 2011 , Page（s）: 98 – 10

[4]Wang, Bin; Xie, Jing; Wang, Qin; Crosstalk-aware channel transmitting scheme for error resilience NoC interconnects, International Conference on Electronics, Communications and Control （ICECC）, 2011 9-11 Sept. 2011 190 - 193

[5]Can Wang, Qin Wang, Jianfei Jiang，“A New Asynchronous Delay-Insensitive Link based on a 1-of-4 LETS Code” ASICCON2011

[6]Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma and Z.G. Mao, “Effective Multi-Standard Macroblock Prediction VLSI Design for Reconfigurable Multimedia Systems”, ISCAS2011

[7]J. Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha, and D. Friedman, “A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons,” IEEE Custom Integrated Circ

[8]J Maria, B Dang, SL Wright, CK Tsang, P Andry, R Polastre, Yong Liu, L Wiggins, and JU Knickerbocker, “3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections,” IEEE Electronic Components and Technology Conference (ECTC), pp. 268-273, 2011.

[9]T. Dickson, Y. Liu, S. Rylov, B. Dang, C. Tsang, P. Andry, J. Bulzacchelli, H. Ainspan, X. Gu,L. Turlapati, M. Beakes, B. Parker, J. Knickerbocker, and D. Friedman, “An 8x10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Intercon

[10]Y. Liu, B. Kim, T. Dickson, J. Bulzacchelli, and D. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” IEEE Solid-State Circuits, Newsletter, Vol. 16, Issue 1, 2011.

[1]Yizhou Xiong, Qin Wang, Jianfei Jiang, Yuliang Tao, Analysis and Mapping of Video Decoding Algorithm on coarse-grain reconfigurable array, IWAC2010

[2]Xiao Cui,Weiguang Sheng,Qin Wang , The Construction and Management of Template Library for Coarse-Grained Reconfigurable System，ICCASM 2010

[3]Jian-Fei Jiang, Zhi-Gang Mao, Wei-Feng He, Qin Wang, "A New Full Adder Design For Tree Structured Arithmetic Circuits", International Conference on Computer Engineering and Technology (ICCET), Vol. 4 , 2010 , Page(s): 246-249

[4]N. Sun, Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “Silicon RF NMR biomolecular sensor - Review," (Invited paper) Proceedings of International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp.121-124, Apr. 2010.

[5]F. Liu, X. Gu, K. A. Jenkins, E. Cartier, Y. Liu, P. Song, and S. J. Koester, “Through-Silicon Via Inductance and Capacitance Characterization,” 60th Electronic Components and Technology Conference (ECTC), June, 2010.

[1]N. Sun, Y. Liu, H. Lee, R. Weissleder, and D. Ham, “CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 5, pp.1629-1643, May 2009.

[2]B. Kim, Y. Liu, T. Dickson, J. Bulzacchelli, and D. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” (Special issue paper) IEEE Journal of Solid-State Circuits (JSSC), vo. 44, no. 12, pp. 3526-3538, Dec. 2009. (JSS

[3]Y. Liu, B. Kim, T. Dickson, J. Bulzacchelli, and D. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” ISSCC Dig. of Tech. Papers, pp. 182-183, Feb. 2009. (Beatrice Winner Award for Editorial Excellence, ISSCC, 200

[1]Y. Liu, S. Nan, H. Lee, R. Weissleder, and D. Ham, “CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing,” ISSCC Dig. of Tech. Papers, pp.140-141, Feb. 2008.

[2]K. Woo, Y. Liu, E. Nam, and D. Ham, “Fast-lock Hybrid PLL Combining Fractional-N & Integer-N Modes of Differing Bandwidths,” IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 2, pp. 379-389, Feb. 2008.

[1]H. Lee, Y. Liu, D. Ham, and R. M. Westervelt, “Integrated cell manipulation system- CMOS/microfluidic hybrid," Lab on a Chip, vol. 7, no. 3, pp. 331-337, March 2007.

[2]Y. Liu, W. Rhee, D. Friedman, and D. Ham, “All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs,” ISSCC Dig. of Tech. Papers, pp.176-177, Feb. 2007.

[3]K. Woo, Y. Liu, and D. Ham, “Fast-lock Hybrid PLL Combining Fractional- & Integer-N Modes of Differing Bandwidths,” Proceedings of IEEE VLSI Symposium, pp. 260-261, June 2007.

[1]H Lee, Y. Liu, R. M. Westervelt, and D. Ham, “IC/Microfluidic Hybrid System for Magnetic Manipulation of Biological Cells,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 6, pp.1471-1480, June 2006.

[2]Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, "CMOS Meets Bio," (Invited paper) Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 419-422, Nov. 2006.

[1]H. Lee, Y. Liu, E. Alsberg, D. E. Ingber, R. M. Westervelt, and D. Ham, “An IC/Microfluidic Hybrid Microsystem for 2D Magnetic Manipulation of Individual Biological Cells,” ISSCC Dig. of Tech. Papers, pp. 80-81, Feb. 2005.

[2]Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “IC/Microfluidic Hybrid System for Biology Applications: Review,” (Invited paper) Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 174-179, Oct. 2005.

[1]Wang Qin，Zhang weijun，Yang Ruqing，“Learning Force based Skill for Robot Tasks in Contact State”，Journal of Beijing Institute of Technology，2004.6

[2]Wangqin,Qian jun, etc, “Robot Programming by Demonstration for Task in Contact State”,Chinese Journal of Mechanical Engineering2004.9.

[3]Wang Qin, etc, “Learning and Merging Robot Performance Skill for Tasks in Contact State”, Journal of Shanghai Jiaotong University, 2004.1

[1]Wang Qin, etc, “Learning Force based Skill of Work in Contact State”, Journal of Shanghai Jiaotong University, 2003. 11

[1]Y. Liu, Z. Gao and X. He, “A Flexible Embedded SRAM Compiler,” Proceedings of IEEE International Workshop on Electronic Design, Test & Applications, pp. 474-476, Jan. 2002.

[2]Y. Liu and Z. Gao, “Timing Analysis of Transistor Stack for Leakage Power Saving,” Proceedings of IEEE International Conference on Electronics, Circuits and Systems, pp. 41-44, Sept. 2002.

[1]Y. Liu, Z. Gao, “A Flexible SRAM Compiler for Embedded Application,” Proceedings of IEEE International Conference on Solid-State and Integrated-Circuit Technology, pp. 213-216, Oct. 2001.