蒋剑飞，博士，副研究员，博士生导师，本科毕业于浙江大学，获工学学士学位，研究生毕业于上海交通大学，获电路与系统工学硕士学位，电子科学与技术工学博士学位。获国家留学基金委《青年骨干教师出国研修项目》资助，2013.7-2014.7期间美国北卡罗莱纳州立大学电子工程系访问学者。获国家外专局资助，2016.10～2016.11期间比利时鲁汶大学和欧洲微电子中心访问学者。

长期从事数字集成电路设计领域的研究，主要研究方向包括高速集成电路、2.5D/3D低功耗集成电路、SoC体系结构、高性能异构计算与神经网络加速电路等。曾承担国家重大专项、国家重点研发等多个重大项目中的芯片课题，在40nm和28nm等工艺下成功流片系列RISC-VSoC与人工智能芯片。近年来，在集成电路领域重要期刊会议上发表SCI/EI论文30余篇，授权国家发明专利10多项。

承担多门专业课程，主持教育部产学合作协同育人项目。曾获“上海交通大学教书育人三等奖”、“上海交通大学教学成果一等奖”。指导本科生获得全国大学生集成电路创新创业大赛全国一等奖4项(其中企业大奖2项)。毕业研究生主要去向：英伟达、华为海思、平头哥、AMD、思科、高通等。

研究方向：

1、高速集成电路

2、2.5D/3D低功耗集成电路

3、SoC体系结构

4、高性能异构计算与神经网络加速电路

[1] K Li, ZZhao, Q Cai, Q Wang, N Jing, Z Mao, JJiang*, “A Novel Vehicle Collision Detection System: Integrating Audio-VisualFusion for Enhanced Performance,” ExpertSystems with Applications, 2024.

[2] L Xie, ZDong, J Sun, S Gao, S Li, N Jing, Q Wang, JJiang*, “A 0.8-ps RMS Precision Period Jitter Measurement Circuit withOffset Reduction,” IEEE InternationalSymposium on Circuits and Systems (ISCAS),2024.

[3] P Liu, ALi, L Chen, J Jiang, Q Wang, Z Mao,N Jing*, “A Comprehensive Dataflow-Mapping Optimization for Fully-PipelinedExecution in Spatial Programmable Architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems, 2024.

[4] N Jing, ZZhang, Y Sun, P Liu, L Chen, Q Wang, JJiang*, “Exploiting Bit Sparsity in Both Activation and Weight in NeuralNetworks Accelerators,” Integration, theVLSI Journal, 2023.

[5] C Yin, J Jiang, Q Wang, Z Mao, N Jing*,“DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs with DeltaUpdating,” IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, 2023.

[6] Z Zhang, J Jiang, Q Wang, Z Mao, N Jing*,“3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator,” IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, 2023.

[7] A Li, J Jiang, Q Wang*, N Jing, Z Dong, S Ji,X Cheng, Y Zhao, “A Method to Improve 3D Interconnections Resource Utilizationand Reliability in Hybrid Bonding Process Considering the Effects on SignalIntegrity,” IEEE 73rd ElectronicComponents and Technology Conference (ECTC),2023.

[8] J Zhang, SCheng, F Dong, K Chen, Y Qiao, Z Mao, JJiang*, “A Hierarchical Communication Algorithm for Distributed DeepLearning Training,” IEEE 66thInternational Midwest Symposium on Circuits and Systems (MWSCAS), 2023.

[9] X Li, ZDong, S Li, S Gao, J Jiang*, G He, ZMao, “MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) StandardBased on gem5,” IEEE 15th InternationalConference on ASIC (ASICON),2023. (Excellent Student Paper)

[10] G Deng, QWang*, J Jiang*, Q Hong, N Jing, WSheng, Z Mao, “A Low Coupling and Lightweight Algorithm for Ship Detection inOptical Remote Sensing Images,” IEEEGeoscience and Remote Sensing Letters, 2022.

[11] J Jiang*, M Jiang, JZhang, F Dong, “A CPU-FPGA Heterogeneous Acceleration System for Scene Text DetectionNetwork,” IEEE Transactions on Circuitsand Systems II: Express Briefs, 2022.

[12] S Li, QWang, J Jiang, W Sheng, N Jing*, ZMao, “An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos onFPGAs,” IEEE Transactions on Very LargeScale Integration (VLSI) Systems, 2022.

[13] Q Wang, FShen, L Cheng, J Jiang*, G He, WSheng, N Jing, Z Mao, “Ship Detection Based on Fused Features and RebuiltYolov3 Networks in Optical Remote-Sensing Images,” International Journal of Remote Sensing, 2021.

[14] J Tu, MLou, J Jiang, D Shu, G He*, “An EfficientMassive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithmto Flexible Architecture,” IEEETransactions on Circuits and Systems I: Regular Papers, 2020.

[15] Q Wang, ZLiu, J Jiang*, N Jing, W Sheng, “A NewCellular-Based Redundant TSV Structure for Clustered Faults,” IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, 2018.

第八届(2024)全国大学生集成电路创新创业大赛，全国一等奖（企业大奖）

第六届(2022)全国大学生集成电路创新创业大赛，全国一等奖（企业大奖）

第五届(2021)全国大学生集成电路创新创业大赛，全国一等奖

第四届(2020)全国大学生集成电路创新创业大赛，全国一等奖

研究方向：数字系统芯片设计
电子邮箱：jiangjianfei@sjtu.edu.cn
办公电话：34204546-1073
办公地点：微电子楼418室