蒋剑飞/助理研究员
个人简介
蒋剑飞，博士，助理研究员，硕士生导师，本科毕业于浙江大学，获工学学士学位，研究生毕业于上海交通大学，获电路与系统工学硕士学位，电子科学与技术工学博士学位。获国家留学基金委《青年骨干教师出国研修项目》资助，2013.7-2014.7 年期间美国北卡罗莱纳州立大学电子工程系访问学者。获国家外专局资助，2016.10～2016.11期间比利时鲁汶大学和欧洲微电子中心访问学者。有十多年数字集成电路设计工作经验，主要从事高速集成电路、三维低功耗集成电路、SoC体系结构与神经网络加速电路、高精度测量电路等方向的设计与研究。曾作为项目主要人员完成多个国家重大项目，包括国家重大专项，863项目，型谱项目和新品项目等，成功设计并流片包括数字信号处理器等多个SoC芯片。在集成电路领域在国内外期刊上发表SCI论文6篇，EI论文19篇，其他论文16篇，国家发明专利多项。
研究方向
1.高速集成电路/高速互连
2.三维低功耗集成电路
3.SoC体系结构与神经网络加速电路
4.高精度测量电路
2.三维低功耗集成电路
3.SoC体系结构与神经网络加速电路
4.高精度测量电路
科研项目
1.国家重大专项，在研;
2.航天基金“面向航天应用的SoC芯片架构与优化研究”， 2015-2017;
3.教育部博士点基金“基于TSV的三维集成电路低功耗设计方法研究”， 2013-2016;
4.总装“XXX IP评测技术与评测电路“，2014-2017;
5.上海市科委“基于国内RF工艺的PDK模型优化研究与推广“，2013-2015。
2.航天基金“面向航天应用的SoC芯片架构与优化研究”， 2015-2017;
3.教育部博士点基金“基于TSV的三维集成电路低功耗设计方法研究”， 2013-2016;
4.总装“XXX IP评测技术与评测电路“，2014-2017;
5.上海市科委“基于国内RF工艺的PDK模型优化研究与推广“，2013-2015。
论文发表
[1] Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao，”Dynamic Data Split: A Crosstalk Suppression Scheme in TSV-Based 3D IC,”Integration, the VLSI Journal 59 (2017) 23–30.
[2] Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wangand Weifeng He, “Delay Analysis and Design Optimization for Low-SwingRC-Limited Global Interconnects,” Journal of Circuits, Systems, and Computers, Vol. 25, No. 10, p1-31, 2016.
[3] Jianfei Jiang, Weifeng He, Qin Wang, Zhigang Mao, “Design Optimization for Capacitive-resistively Driven On-chip Global Interconnect,” IEICE Electronics Express, Vol.12, No.8, p1-12, 2015.
[4] Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao, “Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No.11, p2706-2717, 2015.
[5] Weiguang Sheng, Jianfei Jiang, Zhigang Mao, Parallel SER analysis for combinational and sequential standard cell circuits, Microelectronics Journal, Vol. 50, No. 4, pp. 8-19, 2016.
[6] N Jing, Jiachen Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao, “Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs,”Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 764-769, 2015
[7] Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, “Contactless Testing Methodology for Pre-bondInterposer,” IEEE 58th International Midwest Symposium on Circuits and Systems (MWSWCAS), 2015.
[8] JianFei Jiang, WeiGuang Sheng, Zhigang Mao, Weifeng He, A Pre-emphasis Circuit Design for High Speed On-Chip Global Interconnect, IEEE International Symposium on Circuits and Systems (ISCAS),pp. 2941-2944, 2012.
[9] JianFei Jiang, Xu Wang, WeiGuang Sheng, Wei-feng He, Zhi-gang Mao, A clock-less transceiver for global interconnect, IEEEInternational Conference on VLSI and System-on-Chip (VLSI-SoC),pp.184-187,2011.
[2] Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wangand Weifeng He, “Delay Analysis and Design Optimization for Low-SwingRC-Limited Global Interconnects,” Journal of Circuits, Systems, and Computers, Vol. 25, No. 10, p1-31, 2016.
[3] Jianfei Jiang, Weifeng He, Qin Wang, Zhigang Mao, “Design Optimization for Capacitive-resistively Driven On-chip Global Interconnect,” IEICE Electronics Express, Vol.12, No.8, p1-12, 2015.
[4] Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao, “Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No.11, p2706-2717, 2015.
[5] Weiguang Sheng, Jianfei Jiang, Zhigang Mao, Parallel SER analysis for combinational and sequential standard cell circuits, Microelectronics Journal, Vol. 50, No. 4, pp. 8-19, 2016.
[6] N Jing, Jiachen Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao, “Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs,”Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 764-769, 2015
[7] Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, “Contactless Testing Methodology for Pre-bondInterposer,” IEEE 58th International Midwest Symposium on Circuits and Systems (MWSWCAS), 2015.
[8] JianFei Jiang, WeiGuang Sheng, Zhigang Mao, Weifeng He, A Pre-emphasis Circuit Design for High Speed On-Chip Global Interconnect, IEEE International Symposium on Circuits and Systems (ISCAS),pp. 2941-2944, 2012.
[9] JianFei Jiang, Xu Wang, WeiGuang Sheng, Wei-feng He, Zhi-gang Mao, A clock-less transceiver for global interconnect, IEEEInternational Conference on VLSI and System-on-Chip (VLSI-SoC),pp.184-187,2011.
授课教学
本科生：数字逻辑、Verilog硬件描述语言、先进数字集成电路。
研究生：SoC设计、SystemVerilog电路设计与验证、集成电路基础
研究生：SoC设计、SystemVerilog电路设计与验证、集成电路基础
联系方式
办公地点：微电子大楼418
电子邮箱：jiangjianfei@sjtu.edu.cn
电子邮箱：jiangjianfei@sjtu.edu.cn
