孙亚男/副教授
个人简介
孙亚男博士，现任上海交通大学微纳电子学系副教授。2009年获得上海交通大学微电子学本科学位，2015年获得香港科技大学电子及计算机工程学博士学位，同年加入上海交通大学，从事教学与科研工作。孙亚男博士的主要研究方向是基于新型纳米器件及存储器技术的低功耗高良率集成电路及系统设计，重点关注基于高速互连技术的三维集成电路设计、机器学习及新兴工艺在高可靠性集成电路中的应用。研究成果发表在IEEETCAS-I, TCAS-II,TED, TVLSI, TDMR等国际期刊，以及ISCAS, ISOCC, ICM等国际会议上，曾获2014年IEEE微电子国际会议（ICM）的最佳论文奖。IEEE会员，并担任多个国际期刊和会议的审稿人。自2015年起，担任国际期刊Microelectronics Journal的副主编（Associate Editor）。
Dr. Yanan Sun is currently anAssociate Professor in the Department of Micro-Nano Electronics at Shanghai Jiao Tong University. She received the B.E. degree in Microelectronics from Shanghai Jiao Tong University in 2009, and the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2015.Dr. Sun’s current research is focused on low-power and high-yield integrated circuit and system design with emerging nanoscale transistor and memory technologies (such as carbon nanotube transistors and non-volatile memories). She also has interests in 3D integration circuit design with high-speed interconnect techniques and theapplications of machine-learning/emerging technologies for robust integrated circuits. Her research works are published in the international journals, such as IEEETCAS-I, TCAS-II, TED, TVLSI, and TDMR, as well as the international conferences, such as ISCAS, ISOCC, and ICM. In 2014, she received the best paper award (first place) in the IEEE International Conference on Microelectronics (ICM). Dr. Sun is a member of IEEE. She also served as a reviewer for multiple international journals and conferences. She serves as an associate editor on the editorial boards of the Microelectronics Journalsince 2015.
Dr. Yanan Sun is currently anAssociate Professor in the Department of Micro-Nano Electronics at Shanghai Jiao Tong University. She received the B.E. degree in Microelectronics from Shanghai Jiao Tong University in 2009, and the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2015.Dr. Sun’s current research is focused on low-power and high-yield integrated circuit and system design with emerging nanoscale transistor and memory technologies (such as carbon nanotube transistors and non-volatile memories). She also has interests in 3D integration circuit design with high-speed interconnect techniques and theapplications of machine-learning/emerging technologies for robust integrated circuits. Her research works are published in the international journals, such as IEEETCAS-I, TCAS-II, TED, TVLSI, and TDMR, as well as the international conferences, such as ISCAS, ISOCC, and ICM. In 2014, she received the best paper award (first place) in the IEEE International Conference on Microelectronics (ICM). Dr. Sun is a member of IEEE. She also served as a reviewer for multiple international journals and conferences. She serves as an associate editor on the editorial boards of the Microelectronics Journalsince 2015.
研究方向
1. 基于新型纳米器件的电路与系统设计
2. 新型非易失性存储器及存内计算电路设计
3. 三维集成电路设计
2. 新型非易失性存储器及存内计算电路设计
3. 三维集成电路设计
论文发表
【期刊论文】
[1] Y. Sun, J. Gu, W. He, Q. Wang, N. Jing, Z. Mao, W. Qian, and L. Jiang, "Energy-efficient nonvolatile SRAM design based on resistive switching multi-level cells," IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 66, No. 5, pp. 753-757, May2019.
[2] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, "Metallic-CN-removal-tolerant high-yield six-CNMOSFET SRAM cell for carbon-based embedded memory," IEEE Transactions on Electron Devices (TED), Vol. 65, No. 3, pp. 1230-1238, March 2018.
[3] C. Wang, Y. Sun, S. Hu, L. Jiang, W. Qian, "Variation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit," ACM Transactions on Design Automation of Electronic Systems, Vol. 23, No. 4, pp. 1-27, June 2018.
[4] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, "High-yield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes," IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, pp. 20-31, March 2017.
[5] Y. Sun, W. He, Z. Mao, and V. Kursun, "Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic," Microelectronics Journal (MEJ), Vol. 62, pp. 12-20, February 2017.
[6] Y. Sun, H. Jiao, and V. Kursun, "A novel robust and low-leakage SRAM cell with nine carbon nanotube transistors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
[7] Y. Sun and V. Kursun, "Carbon nanotubes blowing new life into NP dynamic CMOS circuits," IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 2, pp. 420-428, February 2014.
[8] Y. Sun and V. Kursun, "N-type carbon-nanotube MOSFET device profile optimization for very large scale integration," Transactions on Electrical and Electronic Materials, Vol. 12, No. 2, pp. 43-50, April 2011. (invited)
[9] W. Jin, W. He, J. Jiang, H. Huang, X. Zhao, Y. Sun, X. Chen, and N. Jing, "A 0.33V 2.5μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130nm CMOS," Integration, the VLSI Journal, Vol. 58, pp. 27-34, February 2017.
【会议论文】
[1] Y. Lu, Y. Sun*, W. He, and Z. Mao, "A novel memristor-reusable mapping methodology of in-memory logic implementation for high area-efficiency,"Proceedings of the IEEE/ACM International Symposium on Nanoscale Architecture, June 2019.
[2] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, "Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes," Proceedings of the IEEE International Conference on Electronics, Information, and Communication (ICEIC), January 2019.
[3] P. Ji, J. Gao, W. Xu, Y. Sun, W. He, and H. Wu, "Electronic-photonic integrated circuit design and crosstalk modeling for a high density multi-lane MZM array," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
[4] Y. Sun, Wei. He, Z. Mao, H. Jiao, and V. Kursun, "Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors," Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 908-911,October 2017. (invited)
[5] L. Chen, Y. Sun*, and W. He, "Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme," Proceedings of the IEEE International Conferenceon ASIC (ASICON), pp. 916-919,October 2017. (invited)
[6] W. Xu, J. Gao, P. Ji, Y. Sun, W. He, and H. Wu, "A PAM-4 optical receiver based on a silicon photonic quantizer," IEEE International Conference on Group IV Photonics (GFP), pp. 117-118, August 2017.
[7] J. Gao, Y. Sun, W. He, and H. Wu, "A cross-layer multi-physics design flow for electronic-photonic integrated circuits," IEEE Photonics Conference (IPC), pp. 230-231, January 2017.
[8] N. Jing, T. Li, Z. Zhao, W. Jin, Y. Sun, W. He, and Z. Mao, "Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory," International Conference on Field-Programmable Technology (FPT), pp. 233-236, December 2016.
[9] Y. Sun and V. Kursun, "Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.2720-2723, May 2015.
[10] Y. Sun, H. Jiao, and V. Kursun, "Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins," Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014. (Best paper award – first place)
[11]Y. Sunand V. Kursun, “A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 39-42, November 2013.
[12] Y. Sunand V. Kursun, "Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2119-2122, May 2013.
[13] Y. Sunand V. Kursun, "NP dynamic CMOS resurrection with carbon nanotube field effect transistors," Proceedings of the IEEE International SoC Design Conference, pp. 13-16, November 2012.
[14] Y. Sunand V. Kursun, "Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm p-channel MOSFETs," Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 226-231, October 2011.
[15] Y. Sunand V. Kursun, "Substrate bias considerations for low leakage 16nm p-channel carbon nanotube transistors," Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, August 2011.
[16] Y. Sunand V. Kursun, "Uniform diameter and pitch co-design of 16nm n-type carbon nanotube channel arrays for VLSI," Proceedings of the IEEE International Asia Symposium on Quality Electronic Design (ASQED), pp. 211-216, July 2011.
[17] Y. Sunand V. Kursun, "Leakage current and bottom gate voltage considerations in developing maximum performance 16nm n-channel carbon nanotube transistors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2513-2516, May 2011.
[18] Y. Sun and V. Kursun, "Physical parametric analysis of 16nm n-channel carbon-nanotube transistors for manufacturability," Proceedings of the IEEE International Conference on Microelectronics, pp. 28-31, December 2010.
[19] Y. Sun and V. Kursun, "16nm p-type carbon nanotube MOSFET device profile optimization for high-speed," Proceedings of the IEEE International SoC Design Conference, pp. 260-263, November 2010.
Academic Review
International Journals
1. IEEE Transactions on Circuits and Systems I (TCAS-I)2. IEEE Transactions on Circuits and Systems II (TCAS-II)
3. IEEE Transactions on Electron Devices (TED)
4. IEEE Transactions on Very Large Scale Integration (VLSI) Systems
5. IEEE Transactions on Device and Materials Reliability (TDMR)
6. IEEE Journal on Emerging and Selected Topics in Circuits and Systems
7. Microelectronics Journal (MEJ)
8. Integration, the VLSI Journal
9. Journal of Circuits, Systems, and Computers
10. Carbon
International Conferences
1. IEEE International Symposium on Circuits and Systems (ISCAS)
2. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
3. IEEE Asian Solid-State Circuits Conference (A-SSCC)
4. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
5. IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
6. IEEE International System-on-Chip Conference (SOCC)
7. IEEE International Symposium on Quality Electronic Design (ISQED)
8. IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)
9. IEEE International SoC Design Conference (ISOCC)
10. IEEE International Conference on Microelectronics (ICM)
[1] Y. Sun, J. Gu, W. He, Q. Wang, N. Jing, Z. Mao, W. Qian, and L. Jiang, "Energy-efficient nonvolatile SRAM design based on resistive switching multi-level cells," IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 66, No. 5, pp. 753-757, May2019.
[2] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, "Metallic-CN-removal-tolerant high-yield six-CNMOSFET SRAM cell for carbon-based embedded memory," IEEE Transactions on Electron Devices (TED), Vol. 65, No. 3, pp. 1230-1238, March 2018.
[3] C. Wang, Y. Sun, S. Hu, L. Jiang, W. Qian, "Variation-aware global placement for improving timing-yield of carbon-nanotube field effect transistor circuit," ACM Transactions on Design Automation of Electronic Systems, Vol. 23, No. 4, pp. 1-27, June 2018.
[4] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, "High-yield and robust 9T SRAM cell tolerant to removal of metallic carbon nanotubes," IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 17, No. 1, pp. 20-31, March 2017.
[5] Y. Sun, W. He, Z. Mao, and V. Kursun, "Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic," Microelectronics Journal (MEJ), Vol. 62, pp. 12-20, February 2017.
[6] Y. Sun, H. Jiao, and V. Kursun, "A novel robust and low-leakage SRAM cell with nine carbon nanotube transistors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
[7] Y. Sun and V. Kursun, "Carbon nanotubes blowing new life into NP dynamic CMOS circuits," IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 2, pp. 420-428, February 2014.
[8] Y. Sun and V. Kursun, "N-type carbon-nanotube MOSFET device profile optimization for very large scale integration," Transactions on Electrical and Electronic Materials, Vol. 12, No. 2, pp. 43-50, April 2011. (invited)
[9] W. Jin, W. He, J. Jiang, H. Huang, X. Zhao, Y. Sun, X. Chen, and N. Jing, "A 0.33V 2.5μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130nm CMOS," Integration, the VLSI Journal, Vol. 58, pp. 27-34, February 2017.
【会议论文】
[1] Y. Lu, Y. Sun*, W. He, and Z. Mao, "A novel memristor-reusable mapping methodology of in-memory logic implementation for high area-efficiency,"Proceedings of the IEEE/ACM International Symposium on Nanoscale Architecture, June 2019.
[2] Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, "Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes," Proceedings of the IEEE International Conference on Electronics, Information, and Communication (ICEIC), January 2019.
[3] P. Ji, J. Gao, W. Xu, Y. Sun, W. He, and H. Wu, "Electronic-photonic integrated circuit design and crosstalk modeling for a high density multi-lane MZM array," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
[4] Y. Sun, Wei. He, Z. Mao, H. Jiao, and V. Kursun, "Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors," Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 908-911,October 2017. (invited)
[5] L. Chen, Y. Sun*, and W. He, "Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme," Proceedings of the IEEE International Conferenceon ASIC (ASICON), pp. 916-919,October 2017. (invited)
[6] W. Xu, J. Gao, P. Ji, Y. Sun, W. He, and H. Wu, "A PAM-4 optical receiver based on a silicon photonic quantizer," IEEE International Conference on Group IV Photonics (GFP), pp. 117-118, August 2017.
[7] J. Gao, Y. Sun, W. He, and H. Wu, "A cross-layer multi-physics design flow for electronic-photonic integrated circuits," IEEE Photonics Conference (IPC), pp. 230-231, January 2017.
[8] N. Jing, T. Li, Z. Zhao, W. Jin, Y. Sun, W. He, and Z. Mao, "Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory," International Conference on Field-Programmable Technology (FPT), pp. 233-236, December 2016.
[9] Y. Sun and V. Kursun, "Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp.2720-2723, May 2015.
[10] Y. Sun, H. Jiao, and V. Kursun, "Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins," Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014. (Best paper award – first place)
[11]Y. Sunand V. Kursun, “A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 39-42, November 2013.
[12] Y. Sunand V. Kursun, "Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2119-2122, May 2013.
[13] Y. Sunand V. Kursun, "NP dynamic CMOS resurrection with carbon nanotube field effect transistors," Proceedings of the IEEE International SoC Design Conference, pp. 13-16, November 2012.
[14] Y. Sunand V. Kursun, "Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm p-channel MOSFETs," Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 226-231, October 2011.
[15] Y. Sunand V. Kursun, "Substrate bias considerations for low leakage 16nm p-channel carbon nanotube transistors," Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, August 2011.
[16] Y. Sunand V. Kursun, "Uniform diameter and pitch co-design of 16nm n-type carbon nanotube channel arrays for VLSI," Proceedings of the IEEE International Asia Symposium on Quality Electronic Design (ASQED), pp. 211-216, July 2011.
[17] Y. Sunand V. Kursun, "Leakage current and bottom gate voltage considerations in developing maximum performance 16nm n-channel carbon nanotube transistors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2513-2516, May 2011.
[18] Y. Sun and V. Kursun, "Physical parametric analysis of 16nm n-channel carbon-nanotube transistors for manufacturability," Proceedings of the IEEE International Conference on Microelectronics, pp. 28-31, December 2010.
[19] Y. Sun and V. Kursun, "16nm p-type carbon nanotube MOSFET device profile optimization for high-speed," Proceedings of the IEEE International SoC Design Conference, pp. 260-263, November 2010.
Academic Review
International Journals
1. IEEE Transactions on Circuits and Systems I (TCAS-I)2. IEEE Transactions on Circuits and Systems II (TCAS-II)
3. IEEE Transactions on Electron Devices (TED)
4. IEEE Transactions on Very Large Scale Integration (VLSI) Systems
5. IEEE Transactions on Device and Materials Reliability (TDMR)
6. IEEE Journal on Emerging and Selected Topics in Circuits and Systems
7. Microelectronics Journal (MEJ)
8. Integration, the VLSI Journal
9. Journal of Circuits, Systems, and Computers
10. Carbon
International Conferences
1. IEEE International Symposium on Circuits and Systems (ISCAS)
2. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
3. IEEE Asian Solid-State Circuits Conference (A-SSCC)
4. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
5. IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
6. IEEE International System-on-Chip Conference (SOCC)
7. IEEE International Symposium on Quality Electronic Design (ISQED)
8. IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)
9. IEEE International SoC Design Conference (ISOCC)
10. IEEE International Conference on Microelectronics (ICM)
科研项目
目前作为项目负责人，主持国家自然科学基金1项、上海市扬帆计划项目1项。
同时参与国家自然科学基金1项、国家重点研发计划1项。
同时参与国家自然科学基金1项、国家重点研发计划1项。
荣誉奖励
1.上海交通大学电院第二届青年教师教学竞赛-三等奖(英语组), 2018.
2.上海交通大学优秀班主任, 2018.
3. 优秀指导教师奖,北京大学生集成电路设计大赛暨全国邀请赛, 2016.
4. IEEE国际学术会议最佳论文奖,2014.
2.上海交通大学优秀班主任, 2018.
3. 优秀指导教师奖,北京大学生集成电路设计大赛暨全国邀请赛, 2016.
4. IEEE国际学术会议最佳论文奖,2014.
授课教学
本科生：数字集成电路，微纳电子科技前沿讲座
研究生：高等数字集成电路设计，集成电路设计前沿技术
研究生：高等数字集成电路设计，集成电路设计前沿技术
联系方式
办公地点：微电子大楼414室
办公电话：021-34204546-1048
电子邮箱：sunyanan@sjtu.edu.cn
办公电话：021-34204546-1048
电子邮箱：sunyanan@sjtu.edu.cn
