景乃锋/副研究员
个人简介
于上海交通大学计算机科学与技术系获得学士学位，于上海交通大学微电子学院获得硕士和博士学位。曾于美国加州大学洛杉矶分校（UCLA）从事访问交流。
研究方向
研究领域包括高性能计算系统架构及软件协同设计，新型计算芯片架构设计、高可靠性系统设计等
论文发表
1.Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, and Naifeng Jing*, “IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs”, accepted by IEEE Transaction on Parallel and Distributed Systems (TPDS), 29(3): 586-599, 2018.
2.Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang, “CNFET-Based High Throughput SIMD Architecture”, in IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 37(7): 1331-1344, 2018.
3.Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing, “A 0.33 V 2.5 uW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS”, in Integration, the VLSI journal, vol. 58, : 27-34, 2017.
4.Jianfei Wang, Fengfeng Fan, Li Jiang, Xiaoyao Liang and Naifeng Jing*, “Incorporating selective victim cache into GPGPU for high-performance computing”, in Concurrency Computation: Practice and Experience (CCPE), Volume 29, Issue 24, Dec. 2017.
5.Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, and Xiaoyao Liang, “Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 25, issue 2, Feb. 2017, pp. 520-533.
6.Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang, “A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs”, in IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 35(7): 1192-1205, 2016.
7.Naifeng Jing, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, Xiaoyao Liang, “Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs”, in IEEE transactions on computers (TC), volume 64, issue 1, Jan. 2016, pp. 122-135.
8.Tao Zhang, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, Xiaoyao Liang, “Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs”, in ACM Transactions on Architecture and Code Optimization (TACO), 12(2): 16, July 2015.
9.Zhe Feng, Naifeng Jing, Lei He, “IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs”, in IEEE Transaction on Very Large Scale Integration (VLSI) system (TVLSI), volume 22, issue 10, Oct. 2014, pp. 2225-2228.
10.Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao and Lei He, “SEU fault evaluation and characteristics for SRAM-based FPGA architecture and synthesis algorithms”, in ACM Transaction on Design Automation of Electronics System (TODAES), volume 18 issue 1, Jan. 2013.
11.Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang, “Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique”, in Proceedings of the 52nd Annual Design Automation Conference (DAC), June 2017, pp. 38:1-38:6.
12.Xinchi Gao, Licheng Xu, Jing Jin, Naifeng Jing, Jianjun Zhou, “A Wideband Simplified Transformer-Based VCO with Digital Amplitude Calibration”, Gao, Xinchi, et al. "A wideband simplified transformer-based VCO with digital amplitude calibration", International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 787-790.
13.Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang, “CNFET-based high throughput register file architecture.”, in Proceeding of the 34th International Conference on Computer Design (ICCD), Oct. 2016, pp. 662-669.
14.Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He and Zhigang Mao, “Enabling In-Situ Logic-In-Memory Capability Using Resistive-RAM Crossbar Memory”, in Proceeding of the International Conference on Field-Programmable Technology (FPT), Dec. 2016.
15.Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang, “Cache-Emulated Register File: An Integrated On-Chip Memory Architecture for High Performance GPGPUs”, in Proceeding of the 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct. 2016.
16.Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang* and Naifeng Jing*, “Applying Victim Cache in High Performance GPGPU Computing”, in Proceeding of the International Symposium on Parallel and Distributed Computing (ISPDC), July, 2016. (Best paper award)
17.Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao, “Resource-saving compile flow for coarse-grained reconfigurable architectures”, in Proceeding of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), Dec. 2015, pp. 1-8.
18.Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu, “On diagnosable and tunable 3D clock network design for lifetime reliability enhancement”, in Proceeding of the IEEE International Test Conference (ITC), Oct. 2015, pp.1-10.
19.Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian, “Timing-driven placement for carbon nanotube circuits”, in Proceeding of the 28th IEEE International System-on-Chip Conference (SoCC), Sept. 2015, pp. 362-367.
20.Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao, “Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs”, in Proceeding of the 2015 International Conference on Computer-Aided Design (ICCAD), Nov. 2015, pp. 764-769.
21.Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, and Xiaoyao Liang, “Bank Stealing For Conflict. Mitigation in GPGPU Register File”, in Proceeding of the 2015 International Symposium on Low Power Electronics and Design (ISLPED), July. 2015. 22.Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang, “CGSharing: Efficient Content Sharing in GPU-Based Cloud Gaming”, in Proceeding of the 2015 International Symposium on Low Power Electronics and Design (ISLPED), July. 2015.
23.Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang, “Jump test for metallic CNTs in CNFET-based SRAM”, in Proceedings of the 52nd Annual Design Automation Conference (DAC), June 2015, pp. 16:1-16:6
24.Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang, “Compiler Assisted Dynamic Register File in GPGPU”, in Proceeding of the 2013 International Symposium on Low Power Electronics and Design (ISLPED), Sept. 2013, pp. 3-8.
25.Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang, “An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU”, in Proceeding of the 40th International Symposium on Computer Architecture (ISCA), June 2013, pp. 344-355.
2.Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang, “CNFET-Based High Throughput SIMD Architecture”, in IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 37(7): 1331-1344, 2018.
3.Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing, “A 0.33 V 2.5 uW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS”, in Integration, the VLSI journal, vol. 58, : 27-34, 2017.
4.Jianfei Wang, Fengfeng Fan, Li Jiang, Xiaoyao Liang and Naifeng Jing*, “Incorporating selective victim cache into GPGPU for high-performance computing”, in Concurrency Computation: Practice and Experience (CCPE), Volume 29, Issue 24, Dec. 2017.
5.Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, and Xiaoyao Liang, “Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 25, issue 2, Feb. 2017, pp. 520-533.
6.Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang, “A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs”, in IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 35(7): 1192-1205, 2016.
7.Naifeng Jing, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, Xiaoyao Liang, “Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs”, in IEEE transactions on computers (TC), volume 64, issue 1, Jan. 2016, pp. 122-135.
8.Tao Zhang, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, Xiaoyao Liang, “Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs”, in ACM Transactions on Architecture and Code Optimization (TACO), 12(2): 16, July 2015.
9.Zhe Feng, Naifeng Jing, Lei He, “IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs”, in IEEE Transaction on Very Large Scale Integration (VLSI) system (TVLSI), volume 22, issue 10, Oct. 2014, pp. 2225-2228.
10.Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao and Lei He, “SEU fault evaluation and characteristics for SRAM-based FPGA architecture and synthesis algorithms”, in ACM Transaction on Design Automation of Electronics System (TODAES), volume 18 issue 1, Jan. 2013.
11.Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang, “Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique”, in Proceedings of the 52nd Annual Design Automation Conference (DAC), June 2017, pp. 38:1-38:6.
12.Xinchi Gao, Licheng Xu, Jing Jin, Naifeng Jing, Jianjun Zhou, “A Wideband Simplified Transformer-Based VCO with Digital Amplitude Calibration”, Gao, Xinchi, et al. "A wideband simplified transformer-based VCO with digital amplitude calibration", International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 787-790.
13.Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang, “CNFET-based high throughput register file architecture.”, in Proceeding of the 34th International Conference on Computer Design (ICCD), Oct. 2016, pp. 662-669.
14.Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He and Zhigang Mao, “Enabling In-Situ Logic-In-Memory Capability Using Resistive-RAM Crossbar Memory”, in Proceeding of the International Conference on Field-Programmable Technology (FPT), Dec. 2016.
15.Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang, “Cache-Emulated Register File: An Integrated On-Chip Memory Architecture for High Performance GPGPUs”, in Proceeding of the 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct. 2016.
16.Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang* and Naifeng Jing*, “Applying Victim Cache in High Performance GPGPU Computing”, in Proceeding of the International Symposium on Parallel and Distributed Computing (ISPDC), July, 2016. (Best paper award)
17.Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao, “Resource-saving compile flow for coarse-grained reconfigurable architectures”, in Proceeding of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), Dec. 2015, pp. 1-8.
18.Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu, “On diagnosable and tunable 3D clock network design for lifetime reliability enhancement”, in Proceeding of the IEEE International Test Conference (ITC), Oct. 2015, pp.1-10.
19.Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian, “Timing-driven placement for carbon nanotube circuits”, in Proceeding of the 28th IEEE International System-on-Chip Conference (SoCC), Sept. 2015, pp. 362-367.
20.Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao, “Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs”, in Proceeding of the 2015 International Conference on Computer-Aided Design (ICCAD), Nov. 2015, pp. 764-769.
21.Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, and Xiaoyao Liang, “Bank Stealing For Conflict. Mitigation in GPGPU Register File”, in Proceeding of the 2015 International Symposium on Low Power Electronics and Design (ISLPED), July. 2015. 22.Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang, “CGSharing: Efficient Content Sharing in GPU-Based Cloud Gaming”, in Proceeding of the 2015 International Symposium on Low Power Electronics and Design (ISLPED), July. 2015.
23.Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang, “Jump test for metallic CNTs in CNFET-based SRAM”, in Proceedings of the 52nd Annual Design Automation Conference (DAC), June 2015, pp. 16:1-16:6
24.Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang, “Compiler Assisted Dynamic Register File in GPGPU”, in Proceeding of the 2013 International Symposium on Low Power Electronics and Design (ISLPED), Sept. 2013, pp. 3-8.
25.Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang, “An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU”, in Proceeding of the 40th International Symposium on Computer Architecture (ISCA), June 2013, pp. 344-355.
授课教学
本科生：计算机体系结构、组成原理与接口
联系方式
办公地点：上海交通大学闵行校区微电子大楼410室
办公电话： 021-34204546-1074
电子邮箱：sjtuj@sjtu.edu.cn
办公电话： 021-34204546-1074
电子邮箱：sjtuj@sjtu.edu.cn
