绳伟光/助理研究员
个人简介
绳伟光博士现任上海交通大学微电子学院助理研究员。1999年毕业于哈尔滨工业大学电化学工程专业，2004年获哈尔滨工业大学计算机科学与技术专业硕士学位，2009年获哈尔滨工业大学微电子学与固体电子学博士学位，2012年上海交通大学微电子学院博士后出站后留院工作。绳伟光博士目前是ACM会员，中国计算机学会会员，已发表各类论文约20篇，目前主持自然科学基金项目1项，参与863等项目多项。
研究方向
主要研究方向为可重构计算系统及其编译技术、高可靠集成电路设计。
科研项目
1.重大专项“XXX FPGA”，参与，2017-2020。
2.自然科学基金“粗粒度可重构架构的软错误自适应防护模型与方法研究”，项目负责人，2013-2015。
3.十二五863项目“面向通用计算的可重构处理器关键技术研发”，参与，2012-2015。
4.十一五863重点项目“嵌入式可重构移动媒体核心处理技术”，参与，2009-2012。
2.自然科学基金“粗粒度可重构架构的软错误自适应防护模型与方法研究”，项目负责人，2013-2015。
3.十二五863项目“面向通用计算的可重构处理器关键技术研发”，参与，2012-2015。
4.十一五863重点项目“嵌入式可重构移动媒体核心处理技术”，参与，2009-2012。
论文发表
[1] Zhao Z., Liu Y., Sheng W., Krishna T., Wang Q., Mao Z. Optimizing the data placement and transformation for multi-bank CGRA computing system. 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018: 1087-1092.
[2] Zhao Z., Sheng W., He W., Mao Z., Li Z. A static-placement, dynamic-issue framework for CGRA loop accelerator. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017: 1348-1353.
[3] Sheng W. G., Jiang J. F., Mao Z. G. Parallel SER analysis for combinational and sequential standard cell circuits[J]. Microelectronics Journal, 2016,50: 8-19.
[4] Sheng W., Zhao Z., Mao Z. Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC). 2015: 325-326.
[5] Zhao Z., Sheng W., Jing N., He W., Mao Z. Resource-saving compile flow for coarse-grained reconfigurable architectures. 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). 2015: 1-8.
[6]W. Sheng, W. He, J. Jiang, and Z. Mao, "Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm," presented at the 19th Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, 2012.
[7] W. Sheng, L. Xiao, and Z. Mao, "Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm," in Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC'09), 2009, pp. 502-507.
[2] Zhao Z., Sheng W., He W., Mao Z., Li Z. A static-placement, dynamic-issue framework for CGRA loop accelerator. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017: 1348-1353.
[3] Sheng W. G., Jiang J. F., Mao Z. G. Parallel SER analysis for combinational and sequential standard cell circuits[J]. Microelectronics Journal, 2016,50: 8-19.
[4] Sheng W., Zhao Z., Mao Z. Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC). 2015: 325-326.
[5] Zhao Z., Sheng W., Jing N., He W., Mao Z. Resource-saving compile flow for coarse-grained reconfigurable architectures. 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). 2015: 1-8.
[6]W. Sheng, W. He, J. Jiang, and Z. Mao, "Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm," presented at the 19th Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, 2012.
[7] W. Sheng, L. Xiao, and Z. Mao, "Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm," in Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC'09), 2009, pp. 502-507.
授课教学
本科生：C程序与算法设计、算法原理、编译技术与算法设计引论
联系方式
办公地点：微电子学院418
办公电话：021-34204546-1047
电子邮箱：wgshenghit@sjtu.edu.cn
办公电话：021-34204546-1047
电子邮箱：wgshenghit@sjtu.edu.cn
