Talk title: Resilient VLSI Design in Nanometer CMOS and 3D-IC
Speaker: Prof. David Z. Pan
Department of Electrical and Computer Engineering
The University of Texas at Austin, TX 78712
Organizer: Prof. Guoyong SHI
Place: Room 401
Time: 3:00 – 4:00 pm, June 21, 2010
Abstract
In this talk, I will first give a brief overview of the key researches conducted by my group (www.cerc.utexas.edu/utda). Then I will present some key challenges and results in VLSI design for manufacturability (DFM) and reliability in nanometer CMOS and 3D-IC. For 22nm node and below, lithography is facing tremendous challenges and double patterning lithography (DPL) is the forerunner for 22nm/16nm. I will present a novel multi-objective layout decomposition framework that can simultaneously minimize stitches, self-compensate overlay variations, and balance the patterning density [ASPDAC’10 Best Paper Award]. The manufacturability/yield shall be considered during physical design, in particular routing to achieve better solution quality and layout compliance. For nanometer CMOS, aging effect due to NBTI is a serious problem. I will show both design and CAD techniques to compensate the aging effect due to NBTI [DATE’10 Best IP Award, ISPD’10 Best Paper Nominee]. For 3D-ICs, through silicon vias (TSV) cause thermal-mechanical stress effects which affect timing and reliability. We develop the first-order compact model for stress-induced mobility and timing variations, which can be used for TSV and cell layout optimizations.
Biography
David Z. Pan is currently an Associate Professor (with tenure) at the Department of Electrical and Computer Engineering, University of Texas at Austin, where he directs the UT Design Automation (UTDA) Lab. He received his Ph.D. in computer science (with honor) from UCLA in 2000. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His research is mainly focused on design for manufacturing/reliability, nanometer physical design, intersection of physical and system-level co-design, and CAD for emerging technologies. He holds 8 U.S. patents and has published over 120 technical papers in premier journals and international conferences. He has served as an Associate Editor for IEEE Transactions on CAD, IEEE Transactions on VLSI, IEEE Transactions on CAS-I, IEEE Transactions on CAS-II, IEEE CAS Society Newsletter, and Journal of Computer Science and Technology. He has served as the IEEE CANDE Committee Chair, ACM/SIGDA Physical Design Technical Committee Chair, committee member of major VLSI/CAD conferences, including ACISC (Program/General Chair), ASPDAC (Topic Chair), DAC, DATE, ICCAD, GLSVLSI (Publicity Chair), ISCAS (CAD Track Chair), ISLPED (Exhibits Chair), ISPD (Program/General Chair), ISQED (Topic Chair), SLIP (Publication Chair), VLSI-DAT (EDA Chair). He is a member of the International Technology Roadmap for Semiconductor (ITRS). He is a Technical Advisory Board member of Pyxis Technology, Inc.
He has received a number of awards for his research contributions and professional services, including ACM/SIGDA Outstanding New Faculty Award, NSF CAREER Award, UCLA Engineering Distinguished Young Alumnus Award, IBM Faculty Award, SRC Inventor Recognition Award, ACM Recognition of Service Award, Best Paper Award at ASPDAC 2010, Best IP Award at DATE 2010, Best Student Paper Award at ICICDT 2009, Best Paper In Session Award at SRC Techcon (1998 and 2007), ISPD 2007 Global Routing Contest Awards, eASIC Placement Contest Grand Prize (2009), and a number of Best Paper Award Nominations (at ASPDAC, DAC, ICCAD, ISPD). He is an IEEE CAS Society Distinguished Lecturer for 2008–2009.