Date: 2009-6-12
Time: 10:30–11:30am, June 16, 2009
Room: Room 401 of the building of school of microelectronics;
Title: Variational Analysis of Full-Chip Leakage Power in Nanometer VLSI Systems
Speaker: Dr. Sheldon X-.D. Tan
Organizer: Prof. Guoyong Shi
Abstract
The chip performance uncertainties coming from the variability inherent in silicon manufacture process are emerging as the grand challenge to design ICs in nanometer regime. It is important to efficiently estimate the impacts of the variability on chip performance in every design step to ensure high yields. This is the particular case for leakage power, which has increased dramatically with the technology scaling and is becoming the dominant chip power dissipation.
In this talk, I will present a new statistical full-chip leakage power analysis technique, which can derive the full-chip leakage current or power in a closed form in terms of the variational parameters, such as the channel length, the gate oxide thickness, etc. It can accommodate various spatial correlations. The new method can explore the strong special correlations of intra-die variations to speed up the analysis process. The new method employs the orthogonal polynomials to represent the variational gate leakages in a closed form, generated by a fast multi-dimensional Gaussian quadrature method. The proposed method is very efficient and it becomes linear in the presence of strong spatial correlations.
BIOGRAPHY
Dr. Tan is an Associate Professor in the Department of Electrical Engineering, University of California at Riverside. He received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999.
Dr. Tan research interests include several aspects of design automation for VLSI integrated circuits modeling and simulation of analog/RF/mixed-signal VLSI circuits, high performance power and clock distribution network simulation and design, signal integrity, power modeling, architecture-level thermal modeling and simulation, thermal optimization in nanometer VLSI design, and embedded system designs based on FPGA platforms. He has published 2 books, over 130 peer-reviewed journal and conference papers and gave over 30 invited presentations, tutorials and short courses at conferences and workshops.
Dr. Tan received NSF CAREER Award in 2004, and the Outstanding Oversea Investigator Collaboration Award from the NSF of China in 2008. He received the Best Paper Award from 2007 IEEE International Conference on Computer Design (ICCD’07), a Best Paper Award Nomination from 2005 IEEE/ACM Design Automation Conference, the Best Paper Award from 1999 IEEE/ACM Design Automation Conference. He received the UC Regent’s Faculty Fellowship in 2004 and 2006 and COR (committee on Research) Research Fellowship from UCR in 2008. He also co-authored book Symbolic Analysis and Reduction of VLSI Circuits by Springer/Kluwer 2005 and “Advanced Model Order Reduction Techniques for VLSI Designs, by Cambridge University Press 2007. Dr. Tan now is serving as an Associate Editor for three journals: ACM Transaction on Design Automation of Electronic Systems (TODAE), Integration, The VLSI Journal, and Journal of VLSI Design.