Title: Configurable Systems Design-ASIP Methods and the DreamWafer Project
Speaker: Prof. Yvon Savaria, Head of Electrical Engineering department, École Polytechnique de Montréal
Place: School of Microelectronics, Room 401
Time: July 14th, 9:30-10:30 am
ABSTRACT
Application Specific Instruction set Processors (ASIPs) popularized by companies such as Tensilica provide an excellent computational acceleration over regular embedded processors for System on Chip Design.
A group of researchers at École Polytechnique has investigated how to design ASIPs for video, image processing and telecommunication applications. The team has explored the limits of computational acceleration and systematic methods to reach it as well as the use of ASIPs in heterogeneous SoC architectures. It has also explored the impact on the energy efficiency of embedded systems based on ASIPs.
Acceleration factors larger than 1400 have been obtained on some video processing applications. It was also found that the ultimate performance of an algorithm taken from a class of related algorithms is sometimes independent of the time complexity of a software implementation of the same algorithm running on the reference embedded processor.
In another project, the DreamWafer project (http://www.dreamwafer.com/), wafer scale integration is used to implement a configurable system technology that allow going from a set of loose digital circuits to a functional system in a matter of minutes. A so-called WaferIC(TM) has an active surface that detect chips’s pins, report their position to a pattern matching software, running a host computer that then correlate those chip footprints to a system netlist that can be routed and configured in minutes to yield a functional system ready to run. Such systems could be configured and reconfigured at will. The WaferBoard(TM) system based on that technology is very well suited for rapid system prototyping or for a wide range of configurable or reconfigurable system applications. First silicon prototypes of the WaferIC are expected at the fall of 2010 and the first fully functional WaferBoard systems should be assembled in 2011.
The presention will cover both research areas, focusing on lessons learned and possible for future research.
BIOGRAPHY
Yvon Savaria received the B.Ing. and M.Sc.A in electrical engineering from École Polytechnique de Montréal in 1980 and 1982 respectively. He also received the Ph.D. in electrical engineering in 1985 from McGill University. Since 1985, he has been with École Polytechnique de Montréal, where he is currently professor and Chairman of the department of electrical engineering.
He has carried work in several areas related to microelectronic circuits and microsystems such as testing, verification, validation, clocking methods, defect and fault tolerance, high-speed interconnects and circuit design techniques, CAD methods, reconfigurable computing and applications of microelectronics to telecommunications, image processing, video processing, radar signal processing, and digital signal processing acceleration. He holds 15 patents, has published 77 journal papers and 316 conference papers, and he was the thesis advisor of 119 graduate students who completed their studies.
He was the program co-chairman of the 1992 edition and the chairman of the 1993 edition of the IEEE Workshop on Defect and Fault Tolerance in VLSI Systems. He was program co-chairman of ASAP’2006 and the general co-chair of ASAP’2007. He has been working as a consultant or was sponsored for carrying research by CNRC, Design Workshop, Dolphin, DREO, Genesis, Gennum, Hyperchip, LTRIM, Miranda, MiroTech, Nortel, Octasic, PMC-Sierra, Technocap, Tundra and VXP. He is a member of the Regroupement Stratégique en Microélectronique du Québec (RESMIQ), of the Ordre des Ingénieurs du Québec (OIQ), and is the Chairman of the board of CMC Microsystems. He was awarded in 2001 a Canada Research Chair (www.chairs.gc.ca) on design and architectures of advanced microelectronic systems. He also received in 2006 a Synergy Award of the Natural Sciences and Engineering Research Council of Canada.