Time: 15:45-17:00, Oct 12, 2009
Place: Room 104 of the building of school of microelectronics
Title: A 6-bit 1GS/s Asynchronous ADC for Ultra-Wide-Band applications
Speaker: Yang Jing (Ph.D. candidate at UC Berkeley, USA)
Biography:
Jing Yang received her B.S. degree in Automation from Tsinghua University, Beijing, China in 2001, and M.S. degree in Electrical Engineering and Computer Sciences from University of California, Berkeley, USA in 2004. Now she is a Ph.D. candidate in Electrical Engineering and Computer Sciences at UC Berkeley, USA. Her research interests are integrated circuits focused on low power design and novel applications in wireless communication.
Abstract:
The high dynamic range issue for wideband wireless radios systems such as cognitive radios has resulted in a challenge of the front-end design, especially with the requirement of low power and small silicon area. Flexibility and reconfigurability in an RF receiver has to be obtained at the presence of strong interferers. Nevertheless, the /Interference to Signal Ratio/ (ISR) sets an infeasible dynamic range for these applications.
A novel receiver architecture is proposed in this work, which uses moderate analog-to-digital converters and the assistance of digital> signal processing to remove the incredible burden in the analog-to-digital converter circuits. In the proposed architecture, an active interference cancellation in time domain mitigates the strong interferers by exploring the characteristics of wideband reception. The high sampling rate over the relatively narrow band interference and the desired signal provides accurate estimation due to the strong correlation between samples in time domain. Our approach enables high-resolution conversion of the input signal with low-resolution components.
A circuit prototype demonstrating the key component in the proposed concept has been designed, fabricated and measured. An asynchronous 6bit 1GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA). Fabricated in 65nm CMOS with an active area of 0.11mm^2 , it achieves a peak SNDR of 31.5dB at 1GS/s sampling rate and has a power consumption of 6.7mW for the analog, digital processing and biasing network. The test-chip prototype is able to maintain a very high input bandwidth, as will be illustrated in this work, enables the receiver to do wideband reception