RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
The goal of RISC-V workshop is to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. The 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017.
This will be a four-day event broken down as follow.
| Date | Event | Register |
| Monday May 8, 2017 | Introduction to RISC-V. this day long session is intended for those who are new to RISC-V and have yet to be exposed to the RISC-V ISA. The session will consist of presentations from the RISC-V Foundation, some of the original creators of the RISC-V ISA and product presentations from vendors within the RISC-V community | |
| May 9-10, 2017 | These two days will follow our traditional two day format with presentations covering various RISC-V projects underway within the RISC-V community and will include a poster / demo reception on Tuesday evening | |
| Thursday May 11, 2017 | The workshop week will conclude with RISC-V Foundation meetings with attendance restricted to members of the RISC-V Foundation. The day will consist of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups. |
- Conference fee
Day 1 Promotion day ： academic $25 industry $50
Day 2-3 Workshop： academic $25 non-member $149
RISC-V由美国加州大学伯克利分校EECS系的Computer Science Division 始创，是一个为了支持计算机体系结构研究和教育目的而设计的新型指令集架构，有望成为应用于业界开发的标准开放架构，现由RISC-V基金会进行管理和维护。
RISC-V研讨会由RISC-V基金会主办，旨在联合整个RISC-V社团，分享来自世界各地的相关最新RISC-V项目信息，并就该指令集的未来发展达成共识。RISC-V研讨会已成功举办五届，近两届分别于美国麻省理工学院（MIT）和谷歌公司（Google）举行。
第六届RISC-V研讨会首次登陆中国，将于5月8日至11日在上海交通大学闵行校区微电子大楼报告厅举行，由NVIDIA与上海交通大学联合承办。
以下是为期4天的研讨会日程安排：
| 日期 | 活动 | 注册 |
| 星期一2017.5.8 | RISC-V推广日，届时将会邀请业界大牛和RISC-V指令集原创者作精彩演讲，包括RISC架构提出者David Patterson和加州大学伯克利分校ASPIRE实验室主任Krste Asanovic。这一议程特别适合目前尚未熟悉或接触过RISC-V指令集的企业界和学术界同仁，大家可以借此机会全面了解RISC-V指令集及相关前景应用。当日还会进行RISC-V社团供应商的产品巡展。 | |
| 2017.5.9-5.10 | 这两天是自由的技术讨论会，按照传统惯例，将进行涵盖各类RISC-V社团项目的会议报告。RISC-V基金会将会收集文章，然后择优列出报告者名单。 | |
| 星期四2017.5.11 | 研讨会最后将进行RISC-V基金会内部会议，仅限于RISC-V基金会成员。将包括技术及市场委员会成员的交流会晤，推动各个课题组目前的工作进展。 |
第一天推广日–报告人介绍
David Patterson，美国计算机界先驱，曾长期任职于加州大学伯克利分校计算机科学系，他是精简指令集的开创者。David Patterson的研究方向包括 redundant arrays of independent disks (RAID), Network of Workstations (NOW)和大规模并行计算。他与John L. Hennessy合著的《计算机体系结构-量化研究方法》成为计算机科学领域经典教材。
Krste Asanovic， 加州大学伯克利分校电子工程与计算机科学系教授，ASPIRE实验室主任，SiFive联合创始人。主要研究大规模集成电路设计，高效率算法，并行计算与系统开发，低功耗设计等。RISC-V指令集和与之相关的Chisel语言的开发就由他进行主导。
地图指示
诚挚邀请各位企业界和学术界同仁参加本次会议，欢迎报名！
会务费：
第1天推广日：学术界人员 $25 企业界人员 $149
第2-3天 研讨会：学术界人员 $25 非会员 $149
详细咨询请致电34204546-1041 孙老师。
